1419 results found for Electronic Design Automation, displaying items 1 - 20
September 8, 2008
[Web Exclusive] Cadence Comes At Power From Two Perspectives
With a two-pronged approach, Cadence is attempting to enable designers to close the loop on low-power design. At the system level, an enhancement of the InCyte tool acquired through Chip Estimate results in greatly improved chip-level architectural power estimation. Meanwhile, an expansion of the Palladium emulation system provides for dynamic power analysis and cycle-accurate power estimation that is linked to accurate technology libraries and the synthesis flow.
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ED News Staff
September 2, 2008
[Web Exclusive] Collaboration Results In First IEEE 1149.7 cJTAG Semiconductor IP Core
The industry’s first synthesizable IP core that implements the upcoming IEEE 1149.7 cJTAG standard, which will be ratified in early 2009, is available from IPextreme. The IEEE 1149.7 standard will provide designers with powerful extensions to the current IEEE 1149.1 (JTAG) standard, using fewer pins and maintaining compatibility...
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ED News Staff
September 2, 2008
[Web Exclusive] Engineering A Hall Of Famer
Once a year we at Electronic Design ask our readers to stand up and recognize those who have made major contributions to the electronic engineering world. Our “2008 Electronic Design Hall of Fame” is primed to hoist another class of engineer superheroes onto your proverbial shoulders.
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John Arkontaky
August 29, 2008
[Web Exclusive] Yield Enhancement Software To Aid Solar Cell Fabs
Magma Design Automation Inc. is developing a yield enhancement software system customized for solar fabs to improve conversion efficiency, increase yield and reduce the manufacturing costs of solar cells. Magma is collaborating with Pegasus Semiconductor-Solar to refine product specifications and test the new product, based on Magma’s YieldManager software system.
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ED News Staff
August 29, 2008
[Web Exclusive] Audio Engine Codec Library Expands With Dolby Pro Logic Additions
Tensilica’s audio codec library for its Xtensa HiFi 2 Audio Engine has been expanded to include Dolby Pro Logic II and Pro Logic IIx decoders. Both Dolby Pro Logic decoders are essential sound processing technologies employed in home-theater AV receivers. Dolby Pro Logic II creates 5.1-channel surround sound from any stereo movie, music, TV, or game audio source, while Dolby Pro Logic IIx extends the sound experience up to a full 7.1-channel configuration.
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ED News Staff
August 29, 2008
[Web Exclusive] Accellera Rolls New Version of Analog, Mixed-Signal Standard
Accellera’s Board of Directors and Technical Committee members have approved a new version of its Verilog-Analog Mixed-Signal (AMS) standard, Verilog-AMS 2.3, as an Accellera standard for analog and mixed-signal design and simulation. The new Verilog-AMS standard unifies the Verilog-AMS 2.2 specification with the IEEE Std. 1364-2005 or Verilog hardware description language (HDL) standard.
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ED News Staff
August 28, 2008[Leapfrog: First Look] 45-nm Via-Programmable ASICs Add High-Speed I/O Transceivers To Feature Mix
ASIC design starts have plummeted in recent years, and there are many good reasons why. Designs at ultra-deep-submicron process nodes are awfully expensive and getting more so daily as mask costs rise, software content proliferates, and verification takes longer. Meanwhile, the steady rise of application-specific standard products (ASSPs) has also contributed heavily to the ASIC’s marketshare slide. Thus, many designers have turned to alternative...
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David Maliniak
August 18, 2008
[Web Exclusive] User Advisory Group To Guide Open Verification Methodology’s Evolution
The best cooperative efforts in the EDA industry are guided by the collective input of users and technology providers. Those that aren’t tend to be dominated by one or two key players, making them somewhat less than truly cooperative. The Open Verification Methodology (OVM) World community is striving for the former path through its establishment of the OVM Advisory Group (OAG), an organization of distinguished users and ecosystem suppliers.
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ED News Staff
August 18, 2008
[Web Exclusive] PCB Tools Cross-Probe Between Layout And Schematic
Providing a valuable mechanism for design, review, verification, and testing of printed-circuit board (PCB) designs, CircuitSpace Foundation from DesignAdvance Systems now offers cross-probing between layouts and PDF schematics. The new cross-probing capability adds to CircuitSpace’s existing auto-clustering and replication technologies and works seamlessly within Cadence’s Allegro PCB design environment.
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ED News Staff
August 18, 2008
[Web Exclusive] Constraint-Driven Flow Targets PCB High-Density Interconnects
With pin pitches shrinking on FPGAs and other IC packages, many printed-circuit board (PCB) designers—like it or not—are forced to enter the realm of high-density interconnects (HDIs). In response to this trend, Cadence has announced the SPB 16.2 release of its Allegro and OrCAD families of PCB design flow. While the flow has offered constraint-driven design for some time, that capability is now coupled with new features aimed at HDIs.
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ED News Staff
August 18, 2008
[Web Exclusive] DDR3 and DDR2 Memory IP Bolsters SoC Designs
A full range of DesignWare DDR intellectual property (IP) is available for systems-on-a-chip (SoCs) that require an interface to high-performance DDR3, DDR2, and DDR memory subsystems. The DesignWare DDR IP delivers memory system performance of up to 1600 Mbps, which is the maximum data rate of the JEDEC DDR3 specification. The IP includes configurable protocol and memory controllers, integrated mixed-signal PHYs including I/Os, and verification IP.
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ED News Staff
August 18, 2008
[Web Exclusive] Cadence Abandons Its Bid To Buy Mentor Graphics
There will be no merger of Cadence Design Systems and Mentor Graphics after all. Cadence has withdrawn its proposal to acquire all of the outstanding shares of Mentor Graphics’ common stock. Instead, Cadence’s board of directors has authorized a $500 million increase to Cadence’s stock repurchase program.
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ED News Staff
August 14, 2008[TechView: EDA] Model Extractor For CMOS Sports Improved RF/DC Parameters
It’s very difficult to create accurate device-simulation models for advanced CMOS digital processes. Why? Because hard-to-model effects like gate accumulation and tunneling, trap-assisted tunneling, and halo effects have become so prevalent at ultra-deep-submicron technology nodes. For designers of RFcapable systems-on-a-chip (SoCs), this has become a critical issue in the accurate prediction of the behavior of highly nonlinear RF circuits,...
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David Maliniak
August 4, 2008
[NI Week] Get Ready For NIWeek
NI Week 2008 is here. Starting on Tuesday, August 5, more than 3,000 engineers, scientists, educators, and NI developers will convene at the Austin Convention Center in Austin, Texas for three full days of interactive technical sessions, hands-on workshops, case study presentations, and exhibitions on the latest technologies for design, control, and test applications. Hosted by National Instruments, this show is both intellectually stimulating and a lot of fun.
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Louis E. Frenzel
August 4, 2008
[Web Exclusive] FPGA Tools Aid Power Reduction And Simplify Design Creation
The latest revision of Actel’s Libero Integrated Development Environment (IDE) gives designers additional power supply options and enables even lower power consumption. Libero IDE 8.4 offers an FPGA core operating-voltage range from 1.14 to 1.575 V for Actel’s flash-based Igloo, Igloo Plus and ProASIC3L FPGAs. Enhancements to the SmartPower analysis tools within the Libero IBE also ease comparisons of multiple design scenarios and their resulting power consumption and battery life implications.
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Staff
August 4, 2008
[Web Exclusive] Enhancements Bolster RF Board Design Suite
With improvements to the reliability of artwork masks for electromagnetic (EM) verification and RF board manufacturing, the 2008.07 release of Agilent Technologies’ Genesys suite for RF printed-circuit board (PCB) design delivers shorter design cycles with less iteration for RF designers. The update also includes modeling and user-interface enhancements.
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Staff
August 4, 2008
[Web Exclusive] Automotive And Aerospace Designers Gain A Simulator
Simulation functionality is now available to designers of automotive and aerospace electrical systems in the 2008.1 release of Mentor Graphics’ CHS design software. The release makes these capabilities inherently available within the core Capital Logic and Capital Integrator tools.
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Staff
August 4, 2008
[Web Exclusive] Expect New Consumer Electronics Devices Thanks to TLM 2.0
I’m a typical technology-obsessed engineer. I could walk for hours through places like Tokyo’s Akihabara area exploring the latest and greatest consumer electronics devices. It can even be difficult to drag me out of the local big-name electronics store when the latest round of gadgets arrives. It’s always a thrill to see the new and fascinating ways that manufacturers have leveraged technology to create gadgets in an attempt to meet every human need.
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Bill Neifert
August 4, 2008
[Web Exclusive] HF Design Suite Integrates Filter Design Tool
The Microwave Office high-frequency design suite now integrates what’s claimed as a breakthrough in filter design from its partner Nuhertz Technologies. Nuhertz’s filter synthesis and analysis software, Nuhertz Filter, offers what’s termed “delay equalization with off-axis quadruplet and real zeros,” which reduces from hours to seconds the computation time required to obtain flat group delay response in quadruplet-zeros-delay-equalized lumped element filters.
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Staff
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