Author - Arya Raychaudhuri

Technologies
- Analog
- Communications
- Components
- Digital ICs
- EDA
- Embedded
- Power
- Test
Design Hotspots
- Analog
- CDNLive!
- Embedded
- Green Design
- Power
Resources
Magazine
eBooks & Whitepapers
Shows
- NI Week
- MTT-S
- DAC
- MD&M
- PCIM
- SID
- IEF
- ESC
- CTIA
- APEC
- All Shows
Jobs
More...
- eBooks
- Whitepapers
- Webcasts
- Job Zone
- Newsletters
- Blogs
- Hall of Fame
- RSS
- Subscribe

Click to view this week's ad screen

Arya Raychaudhuri	Write for Electronic Design
Arya Raychaudhuri, senior staff design engineer with Fastrack Design in San Jose, Calif., has been working in physical design verification and extraction with Calibre software and the Calibre DesignRev tool for 10 years. He holds a PhD in CMOS device physics and modeling.
2 results found for Arya Raychaudhuri, displaying items 1 - 2

June 10, 2008 [Design View / Design Solution]
Correct-By-Construction Layout Generation And Modification
Physical design verification software typically identifies faults in physical layouts by finding design-rule-check (DRC) violations and layout-versus-schematic (LVS) mismatches after layout is complete. So-called “correct-by-construction” layout generation is a method for generating and modifying polygonal features during the layout construction process so that the layout satisfies both design-rule constraints and connectivity requirements.

June 10, 2008 [Design View / Design Solution]
About Polygon Processing Engines
Correct-by-construction polygon processing capabilities, which together are commonly called a polygon processing engine (PPE), enable a physical designer to perform all forms of layout transformation in a post-stream-out GDS database.